Namespaces | Macros | Functions | Variables
simd.h File Reference

SIMD-type algorithms, with hardware acceleration, if available. More...

#include "ulimits.h"
#include <math.h>

Namespaces

 ustl
 The ustl namespace contains all ustl classes and algorithms.
 

Macros

#define SIMD_PACKEDOP1(name, operation)
 
#define SIMD_PACKEDOP2(name, operation)
 
#define SIMD_PACKEDOP3(name, operation)
 
#define SIMD_SINGLEOP1(name, operation)
 
#define SIMD_CONVERTOP(name, operation)
 
#define VECTOR_ATTRIBUTE(mode, vs)
 
#define SIMDA_RI(n)   "m"(oin[n])
 
#define SIMDA_RO(n)   "m"(oout[n])
 
#define SIMDA_WI(n)   "=m"(oin[n])
 
#define SIMDA_WO(n)   "=m"(oout[n])
 
#define SIMD_PKOP2_SPEC(n, type, optype)
 
#define SIMD_PASSIGN_SPEC(n, type)
 
#define SIMD_IPASSIGN_SPEC(n, type)
 
#define SIMD_CONVERT_SPEC(n, type1, type2, optype)
 
#define STD_MMX_ARGS   : "m"(oout[0]), "m"(oin[0]) : "mm0", "st", "memory"
 
#define DBL_MMX_ARGS   : "m"(oout[0]), "m"(oout[2]), "m"(oin[0]), "m"(oin[2]) : "mm0", "mm1", "st", "st(1)", "memory"
 
#define MMX_PKOP2_SPEC(n, type, optype, instruction)
 
#define MMX_DBL_PKOP2_SPEC(n, type, optype, instruction)
 
#define MMX_PASSIGN_SPEC(n, type)
 
#define MMX_DBL_PASSIGN_SPEC(n, type)
 
#define MMX_IPASSIGN_SPEC(n, type)
 
#define MMX_DBL_IPASSIGN_SPEC(n, type)
 
#define STD_SSE_ARGS   : "m"(oout[0]), "m"(oin[0]) : "xmm0", "memory"
 
#define SSE_PKOP2_SPEC(n, type, optype, instruction)
 
#define SSE_PASSIGN_SPEC(n, type)
 
#define SSE_IPASSIGN_SPEC(n, type)
 

Functions

template<typename Ctr , typename UnaryOperation >
void ustl::simd::packop (Ctr &op1, UnaryOperation op)
 Applies op to each element in op1.
 
template<typename Ctr , typename BinaryOperation >
void ustl::simd::packop (const Ctr &op1, Ctr &op2, BinaryOperation op)
 Applies op to each element in op1 and op2 and stores in op2.
 
template<typename Ctr , typename BinaryOperation >
void ustl::simd::packop (const Ctr &op1, const Ctr &op2, Ctr &result, BinaryOperation op)
 Applies op to corresponding elements in op1 and op2 and stores in result.
 
template<typename Ctr >
void ustl::simd::passign (const Ctr &op1, Ctr &result)
 Copies op1 into result.
 
template<typename Ctr >
void ustl::simd::ipassign (typename Ctr::const_iterator op1, Ctr &result)
 Copies result.size() elements from op1 to result.
 
template<typename Ctr1 , typename Ctr2 , typename ConvertFunction >
void ustl::simd::pconvert (const Ctr1 &op1, Ctr2 &op2, ConvertFunction f)
 
 ustl::simd::STD_BINARY_FUNCTOR (fpadds, T,((b > numeric_limits< T >::max()-a)?numeric_limits< T >::max():a+b)) STD_BINARY_FUNCTOR(fpsubs
 

Variables

 ustl::simd::T
 

Detailed Description

SIMD-type algorithms, with hardware acceleration, if available.

All algorithms are container-based because iterator syntax is just too damn verbose and because the specializations need to be able to tell how many elements are in the container in order to choose proper SIMD instruction set (i.e.: 4 floats select SSE, while 2 floats select 3dNow!) Specializations are only for the tuple template because the container must be of a fixed and compile-time-known size for the compiler to be able to choose the specialization.

Macro Definition Documentation

#define MMX_DBL_IPASSIGN_SPEC (   n,
  type 
)
Value:
SIMD_IPASSIGN_SPEC(n,type) \
{ asm ("movq %2, %%mm0\n\tmovq %3, %%mm1\n\tmovq %%mm0, %0\n\tmovq %%mm1, %1" : DBL_MMX_ARGS); reset_mmx(); }
#define MMX_DBL_PASSIGN_SPEC (   n,
  type 
)
Value:
SIMD_PASSIGN_SPEC(n,type) \
{ asm ("movq %2, %%mm0\n\tmovq %3, %%mm1\n\tmovq %%mm0, %0\n\tmovq %%mm1, %1" : DBL_MMX_ARGS); reset_mmx(); }
#define MMX_DBL_PKOP2_SPEC (   n,
  type,
  optype,
  instruction 
)
Value:
SIMD_PKOP2_SPEC(n,type,optype) \
{ asm ("movq %0, %%mm0\n\tmovq %1, %%mm1\n\t" #instruction " %2, %%mm0\n\t" #instruction " %3, %%mm1\n\tmovq %%mm0, %0\n\tmovq %%mm1, %1" : DBL_MMX_ARGS); reset_mmx(); }
#define MMX_IPASSIGN_SPEC (   n,
  type 
)
Value:
SIMD_IPASSIGN_SPEC(n,type) \
{ asm ("movq %1, %%mm0\n\tmovq %%mm0, %0" : STD_MMX_ARGS); reset_mmx(); }
#define MMX_PASSIGN_SPEC (   n,
  type 
)
Value:
SIMD_PASSIGN_SPEC(n,type) \
{ asm ("movq %1, %%mm0\n\tmovq %%mm0, %0" : STD_MMX_ARGS); reset_mmx(); }
#define MMX_PKOP2_SPEC (   n,
  type,
  optype,
  instruction 
)
Value:
SIMD_PKOP2_SPEC(n,type,optype) \
{ asm ("movq %0, %%mm0\n\t" #instruction " %1, %%mm0\n\tmovq %%mm0, %0" : STD_MMX_ARGS); reset_mmx(); }
#define SIMD_CONVERT_SPEC (   n,
  type1,
  type2,
  optype 
)
Value:
template <> \
inline void pconvert (const tuple<n,type1>& oin, tuple<n,type2>& oout, optype<type1,type2>)
#define SIMD_CONVERTOP (   name,
  operation 
)
Value:
template <typename Ctr1, typename Ctr2> \
inline void name (const Ctr1& op1, Ctr2& op2) \
{ \
typedef typename Ctr1::value_type value1_t; \
typedef typename Ctr2::value_type value2_t; \
pconvert (op1, op2, operation<value1_t, value2_t>());\
}
#define SIMD_IPASSIGN_SPEC (   n,
  type 
)
Value:
template <> \
inline void ipassign (tuple<n,type>::const_iterator oin, tuple<n,type>& oout)
#define SIMD_PACKEDOP1 (   name,
  operation 
)
Value:
template <typename Ctr> \
inline void name (Ctr& op1) \
{ \
typedef typename Ctr::value_type value_t; \
packop (op1, operation<value_t>()); \
}
#define SIMD_PACKEDOP2 (   name,
  operation 
)
Value:
template <typename Ctr> \
inline void name (const Ctr& op1, Ctr& op2) \
{ \
typedef typename Ctr::value_type value_t; \
packop (op1, op2, operation<value_t>()); \
}
#define SIMD_PACKEDOP3 (   name,
  operation 
)
Value:
template <typename Ctr> \
inline void name (const Ctr& op1, const Ctr& op2, Ctr& result) \
{ \
typedef typename Ctr::value_type value_t; \
packop (op1, op2, result, operation<value_t>()); \
}
#define SIMD_PASSIGN_SPEC (   n,
  type 
)
Value:
template <> \
inline void passign (const tuple<n,type>& oin, tuple<n,type>& oout)
#define SIMD_PKOP2_SPEC (   n,
  type,
  optype 
)
Value:
template <> \
inline void packop (const tuple<n,type>& oin, tuple<n,type>& oout, optype<type>)
#define SIMD_SINGLEOP1 (   name,
  operation 
)
Value:
template <typename T> \
inline T name (T op) \
{ \
operation<T> obj; \
return obj(op); \
}
#define SSE_IPASSIGN_SPEC (   n,
  type 
)
Value:
SIMD_IPASSIGN_SPEC(n,type) \
{ asm ("movups %1, %%xmm0\n\tmovups %%xmm0, %0" : STD_SSE_ARGS);}
#define SSE_PASSIGN_SPEC (   n,
  type 
)
Value:
SIMD_PASSIGN_SPEC(n,type) \
{ asm ("movups %1, %%xmm0\n\tmovups %%xmm0, %0" : STD_SSE_ARGS);}
#define SSE_PKOP2_SPEC (   n,
  type,
  optype,
  instruction 
)
Value:
SIMD_PKOP2_SPEC(n,type,optype) \
{ asm ("movups %0, %%xmm0\n\tmovups %1, %%xmm1\n\t" #instruction " %%xmm1, %%xmm0\n\tmovups %%xmm0, %0" : STD_SSE_ARGS);}

Generated on Mon Sep 28 2015 17:58:50 for uSTL by Doxygen 1.8.10